Physical design and sign-off is the stage that turns a chip's checked design into a drawing that a factory can manufacture: every transistor placed, every wire drawn, and every timing and power figure checked. It is the last stage before tape-out, the moment the final files go to the factory.
It begins with synthesis. A synthesis tool reads the design, which is written as code in a language such as Verilog. It turns the code into a netlist. A netlist is a list of logic gates and the connections between them. A logic gate is a small circuit, made of a few transistors, that computes a simple function such as AND or OR. A transistor is a tiny electrical switch.
Next comes floorplanning: deciding where each large block sits on the chip, and where the power enters. Then placement puts every gate in an exact position. Routing draws the wires between them. A modern chip has more than ten layers of metal wiring stacked above the transistors. The wires on the lowest layers are only a few tens of nanometres wide, and a nanometre is a billionth of a metre. The factory's design rules say, for example, how close two wires may be. The tools must obey every rule.
Then comes sign-off, the final set of checks. Timing analysis checks that every signal reaches its destination within one clock cycle, one tick of the chip's internal clock. Power analysis checks that no area draws so much current that its supply voltage sags. Physical checks confirm that the layout follows every design rule of the factory, and that it matches the netlist exactly.
Consider an engineer at a design centre in Bengaluru working on the processor block of a phone chip. The block holds about 50 crore transistors and must run at 3 gigahertz, so each clock cycle lasts about 333 picoseconds. A picosecond is a millionth of a millionth of a second. After routing, timing analysis finds 1,200 paths on which the signal arrives late. The worst is late by 18 picoseconds. The engineer enlarges some gates, so that they switch faster, and moves others closer together, which shortens their wires. The tools route the block again overnight. The next run finds no late paths, and the power check shows that the voltage drop is within the limit. The block is signed off and merged into the full chip.
Physical design starts from blocks that have passed chip design verification, and it runs in electronic design automation (EDA) software. Its final files, in a format called GDSII or OASIS, go to the semiconductor foundry. The foundry uses them to make a mask for each layer, a plate that carries that layer's pattern. AI for chip design now tunes the tools' settings to find better layouts faster. Physical design is the last step of the VLSI design flow before manufacture.