Chip design verification is the work of running a chip's design in software to prove that it behaves correctly before it is manufactured. It is often the largest part of chip design. On a big chip, there can be more verification engineers than design engineers.
Why so much effort? A chip cannot be patched like an app. Once the factory has made it, its circuits are fixed. A mistake found after manufacture means changing the design and making new masks, the patterned plates used to print the chip's layers. That can cost months and tens of crores of rupees. So the team tries to find every mistake while the chip is still code.
The design is written in a hardware description language, such as Verilog. Verification engineers write a second program around it, called a testbench. The testbench sends inputs into the design, the way the rest of the chip or the outside world would. It then checks every output against what the chip's specification says. Most testbenches are written in SystemVerilog, following a standard method called UVM. The tests use random inputs within set limits, so that they reach situations nobody thought to write by hand.
How does the team know it has tested enough? It measures coverage. Coverage is a record of which situations the tests have actually reached, such as every state of every circuit and every case the specification lists. The team aims for close to 100%.
Take, for example, a verification team of 15 engineers in Noida, checking the block of a Wi-Fi chip that receives data packets. Every night, the team's automated tests run again as a regression: 20,000 tests on a farm of 500 servers. A regression is the full set of earlier tests, run again after every change, so that a new fix does not break something that used to work. By morning, 19,980 tests pass and 20 fail. Sixteen of the failures have one cause. When two packets arrive in the same clock cycle, the block drops the second one. A clock cycle is one tick of the chip's internal clock, here one billionth of a second. The designer fixes the code that day. Coverage now stands at 97%. The team writes new tests for the missing 3%, which are mostly rare error cases.
Simulation is slow for a whole chip. One second of the real chip's work can take weeks to simulate. So, to test the full chip, the team moves to hardware emulation, which runs the design thousands of times faster. When a block is fully verified, it goes on to physical design and sign-off. AI for chip design now helps engineers write tests and trace failures. All of this runs in electronic design automation (EDA) software, and much of the world's chip verification is done in India's design centres.