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AI and data centre chips

Every chatbot answer worked out on boards of GPUs.

1 Question arrives2 CPU prepares it3 GPUs compute4 GPUs share results5 Answer sent, savedpasses it to the serversends tokens to GPUsexchange partial resultssend the answer backNetworking chips+CPU+GPU+High-bandwidthmemory (HBM)+AI accelerator+Custom AI ASIC+Chip interconnect+Hard disk drive (HDD)+Data centre switchesand routers↗ DATA CENTRESLarge languagemodel (LLM)↗ GENERATIVEAI APPLICATIONSAI clusters andrack-scale systems↗ DATA CENTRESGPU cloud↗ CLOUD HOSTINGA lawyer using a chatbot built by astart-up in GurugramThe answer on her screen, and theconversation savedMonths earlier: the model was trained on thousands of GPUs working together, a job that took weeks.CONCEPTS IN THIS SCENEAI acceleratorsMemory wallTraining vs inferenceVendor lock-inDesign winCPU, GPU, SoC and FPGABandwidth and latencyMemory chip cycleFabless chip designInstruction set architecture (ISA)RISC-VSemiconductor IP licensing1 Question arrives2 CPUprepares it3 GPUs compute4 GPUsshare results5 Answersent, savedpasses it to the serversends tokens to GPUsexchange partial resultssend the answer backNetworkingchips+CPU+GPU+High-bandwidthmemory (HBM)+AIaccelerator+CustomAI ASIC+Chipinterconnect+Hard diskdrive (HDD)+Data centreswitchesand routers↗ DATA CENTRESLarge languagemodel (LLM)↗ GENERATIVEAI APPLICATIONSAI clustersand rack-scalesystems↗ DATA CENTRESGPU cloud↗ CLOUD HOSTINGA lawyer using achatbot built by astart-up in GurugramThe answer on herscreen, and theconversation savedMonths earlier: the model was trained on thousands of GPUs working together, a job that took weeks.CONCEPTS IN THIS SCENEAI acceleratorsMemory wallTraining vs inferenceVendor lock-inDesign winCPU, GPU, SoC and FPGABandwidth and latencyMemory chip cycleFabless chip designInstruction set architecture (ISA)RISC-VSemiconductor IP licensingA lawyer using a chatbot builtby a start-up in Gurugram1 Question arrivesNetworking chips+Data centre switches and routers↗ DATA CENTRES↓ passes it to the server2 CPU prepares itCPU+Large language model (LLM)↗ GENERATIVE AI APPLICATIONS↓ sends tokens to GPUs3 GPUs computeGPU+High-bandwidth memory (HBM)+AI accelerator+Custom AI ASIC+AI clusters and rack-scale systems↗ DATA CENTRESGPU cloud↗ CLOUD HOSTING↓ exchange partial results4 GPUs share resultsChip interconnect+↓ send the answer back5 Answer sent, savedHard disk drive (HDD)+→ The answer on her screen, and the conversation savedMonths earlier: the model was trained onthousands of GPUs working together, a job thattook weeks.CONCEPTS IN THIS SCENEAI acceleratorsMemory wallTraining vs inferenceVendor lock-inDesign winCPU, GPU, SoC and FPGABandwidth and latencyMemory chip cycleFabless chip designInstruction set architecture (ISA)RISC-VSemiconductor IP licensing
A lawyer's question to a chatbot passes through a switch chip, the server's CPU, the GPUs with their stacked memory and the links between them, and the answer is sent back and saved on hard drives.
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AI and data centre chips are the chips inside the servers that train AI models and answer every question sent to an AI chatbot. A chip is a small, flat piece of silicon that carries billions of transistors. A transistor is a microscopic electrical switch, and a chip computes by turning its transistors on and off. In a data centre, these chips sit on boards inside servers, and thousands of servers are joined so that they can work on one model together.

Take, for example, a legal-research chatbot built by a start-up in Gurugram. A lawyer types a question: "Can a landlord evict a tenant without notice?" The start-up owns no servers. It rents GPU servers from a GPU cloud provider in a data centre in Chennai, and it pays for every hour it uses them. Here is what happens to the question in the next few seconds.

First, the question arrives at the data centre over the internet. A data centre switch passes it to the right server. Inside the switch, a networking chip reads the address on each piece of data and sends it out through the right port.

Second, the server's CPU, its general-purpose processor, receives the question. The CPU runs the operating system and the start-up's software. It cuts the question into tokens, the small pieces of words that a large language model reads, and sends them to the GPUs.

Third, the GPUs work out the answer. A GPU is a processor with thousands of small cores that do the same arithmetic at the same time. The model itself is a very large set of numbers, called weights. Say the model has 70 billion weights. Stored at 2 bytes each, they take about 140 GB, so they are split across two or more GPUs. Each GPU keeps its share in high-bandwidth memory (HBM), memory chips stacked right beside it. The model writes the answer one token at a time, and for every token each GPU must read all of its weights again. So the speed of the memory decides the speed of the answer. This limit is called the memory wall.

Fourth, the GPUs exchange their partial results through chip interconnect, the fast links that join one processor to the next. This exchange happens for every token, so slow links leave the GPUs waiting.

Fifth, the finished answer goes back to the lawyer, a few seconds after she asked. The conversation is saved on hard disk drives, the cheapest storage for large amounts of data.

The same job can run on other chips. An AI accelerator is a newer chip designed only for AI arithmetic, and several start-ups hope it will cost less per answer. The largest cloud companies, most of them based in the United States, also design their own custom AI chips. Answering questions with a trained model is called inference. Teaching the model in the first place is called training, and the page on training vs inference explains the difference.

Almost none of these chips are made in India. They are designed by fabless companies, which design chips but do not make them, and they are made mostly in Taiwan. But much of the design work is done by engineers in Bengaluru, Hyderabad and Pune.

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