A home Wi-Fi router has a chip that receives radio signals, sorts packets and sends them to the right phone or laptop, many times faster than any program could do on a general processor. Designers built that chip.
Design engineers wrote the logic for each block, such as the part that checks every packet for errors, in Verilog, describing what happens on every tick of the clock. Verification engineers built test environments in SystemVerilog that throw every kind of packet at the design in simulation, running the design as a program on a computer, including broken and unlikely ones, and checked that every corner of the logic had been tried. When a test failed, they read the waveforms, pictures of how signals change over time, in a tool like Synopsys Verdi to find the exact clock tick where it went wrong. Before the real chip existed, the design ran on an FPGA, a chip whose logic can be reprogrammed after it is made, so the router's firmware team could start testing their code on it. Physical design engineers then placed the chip's tiny parts and wires, and the files went to a foundry, the factory that manufactures chips, to be made.
The work involves getting a chip's design right before it is made, and verification is where the effort piles up. A verification engineer's week might hold writing tests for a new feature, running large simulations overnight, chasing a failure through waveforms, and meeting the design engineers to agree whether a behaviour is a bug or a feature of the specification. Design engineers spend their weeks on logic, timing and power, making sure every signal arrives in time and the chip does not run hot. Tools from companies such as Cadence and Synopsys run all of it, and engineers call them EDA tools, short for electronic design automation.
Around the design and verification sits a set of duties that every chip designer shares.
Coverage is tracked closely. Teams measure which parts of the design their tests have reached, and a chip is not signed off until the gaps are closed or explained. Senior engineers review the design and the test plan of each block at set points along the way.
Scripting holds the work together. Engineers write Python, Perl or Tcl scripts to run huge batches of simulations, collect the results and drive the EDA tools. They also share a farm of computers for those simulations and the licences for expensive tools, such as the Synopsys VCS and Cadence Xcelium simulators or the Synopsys Fusion Compiler and Cadence Innovus tools that lay out the chip, and both need managing.
The work carries on after the chip comes back from the factory. Engineers bring up the new chips in the lab, compare their behaviour with the simulations, and help the firmware team when something does not match. Each block also gets a written specification, so that other teams can use it correctly.
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The ideal candidate enjoyed digital electronics, thinks in clock cycles and logic gates, and likes precise work where everything must be checked. It draws on electronics and electrical engineering, and freshers usually come in through a campus programme or a design-services firm. With experience, engineers lead the verification of a whole chip, become architects who decide what a chip should do, or specialise in areas such as low-power design or high-speed interfaces like PCIe.