A chip is written before it is built, in a hardware description language that says what the logic does on every clock tick. Verilog and SystemVerilog are the two named most, about equally, and most job posts that name one name both. Verilog is the older language for describing the design itself. SystemVerilog extends it and is the language of verification, where a test environment is built around the design to drive it with every case it must handle. VHDL is the other design language, named in a fair share of job posts and most at the design-services firms and the tool makers, where older or European-origin designs are maintained. The design under description is an ASIC, a custom chip made once at a foundry, or an FPGA, a chip whose logic can be reprogrammed after it is made. Both are named in a large share of job posts. FPGA leads at the processor makers, where one company sells FPGAs, and at the networking equipment makers, which put FPGA logic inside their switches and routers; ASIC leads at the networking companies and the design-services firms. SoC, a system on a chip, names the whole assembly of processor, memory and peripherals that a modern design is.

Most of the engineering effort on a chip goes into proving the design is correct before it is made, because a mistake found after manufacture costs months and millions. Verification is the largest kind of work in the job posts, and at the company that licenses its processor designs rather than making chips, it is nearly the whole of the work. SystemVerilog is its language, and UVM, the universal verification methodology that structures a test environment, is described in the text of job posts rather than named as a skill. Synopsys Verdi is the tool for debugging a simulation, watching the waveforms to find where the logic went wrong, and it is named most at the processor makers and the design-services firms. Testing is tagged on a large share of job posts, and on most at the processor makers and design-services firms, and here it means simulation, coverage and the bench. C/C++ is the most-named skill in the whole role, which surprises until one sees why: verification environments drive the design with models written in C/C++, and the firmware that first runs on a new chip is written in it too, so the engineer who verifies a processor is expected to write both.

A chip is designed, simulated and laid out in electronic design automation software, and the tools are a skill in their own right. EDA is named in a large share of job posts, and Cadence is the tool maker named most, with Synopsys Verdi as the named Synopsys tool. CAD and engineering software is the most common extra tag in the role, on most job posts, which is the taxonomy's way of saying the engineer lives in these tools. The two tool makers are also the largest single employer of chip designers, because they hire designers and verification engineers to build and test the IP blocks they license, and their job posts name SystemVerilog, EDA and Verilog above everything else, with C/C++ on nearly all of them.

A chip's logic is largely about moving data in and out, and the interfaces are named. PCIe is the most-named, the high-speed link between a processor and its cards, and it leads at the processor makers and the connectivity-chip companies. Ethernet is next, at the networking companies and connectivity-chip makers. USB, SPI, I2C, UART and DMA appear in smaller shares, the same buses a firmware engineer drives but here designed rather than programmed. NVMe and SSD appear at the memory and storage-controller companies. The processor architectures appear too: ARM, named in a fair share, RISC-V, the open architecture used at the processor makers and design-services firms, and x86 at the processor makers. Assembler is named at the processor makers, where the engineer writes the first instructions a new processor runs. At the networking companies the design is a network chip, and MPLS, QoS, Multicast, VXLAN, Layer 2 and Layer 3 name the protocols the silicon has to process at line speed.

The job posts show how far chip work now overlaps with the software beside it. The Linux Kernel, Linux Device Drivers, Embedded Linux and Linux BSP are named in a fair share of job posts across every cohort, because a new chip is not finished until Linux boots on it, and the engineers who bring up a board, write the first drivers and prove the hardware against real software sit beside the designers and are often the same people. QEMU and KVM appear at the processor makers for running software against a model of the chip before the chip exists. GDB, an Oscilloscope, a Logic Analyzer and JTAG are the bench tools for the same work. Compilers appear at the tool makers and processor makers, where the instruction set and the compiler are designed together.

Build and release is tagged on a fair share of job posts, most at the design-services firms and the processor makers, and it means the scripted flows that run simulations and builds, with GitHub Actions and Azure DevOps named where a pipeline carries them, Docker in a few, and Git throughout. Cloud, machine learning on the device and security each appear on a small share of job posts, the last as Secure Boot and ISO 26262 where the chip goes into a car. In the ordinary chip-design job these are a plus.

Underneath all of it sits the way chips are made: a specification, a design written and reviewed, a verification plan with coverage goals that must be met before sign-off, a tape-out date that cannot slip, and then bring-up in the lab when the silicon returns. Job posts count these as given and rarely list them as skills.

A chip designer who writes Verilog and SystemVerilog, can build and debug a verification environment in Synopsys Verdi, knows PCIe and Ethernet well enough to design or verify an interface, understands ARM or RISC-V, works fluently in Cadence and the other EDA tools, and can write the C/C++ that drives a model or boots a board, meets the core of nearly every job post. The variations belong to the employer. The processor makers want FPGA and ASIC design and verification with PCIe, ARM, RISC-V, Assembler and the most bring-up work, and they are the most senior. The company that licenses its designs wants verification above all, in SystemVerilog. The memory and storage-controller companies want staff-level designers with NVMe. The tool makers want SystemVerilog, Verilog, VHDL and EDA to build and verify licensed IP, and they take juniors more readily than most. The networking companies want FPGA and ASIC logic that processes Ethernet, MPLS and VXLAN at line speed. The design-services firms, the classic first door for Indian VLSI engineers, ask for the whole set, VHDL and Cadence included, and have gone quiet. Across all of them, the engineer who can describe logic, prove it right and then watch it boot is the one every job post describes.